It is often necessary in linear mixed-signal CMOS and BiCMOS integrated circuit devices to merge low-voltage (0.8-1.5 volts, for example) and high-voltage (1.8-5 volts, for example) CMOS devices. Generally, the low-voltage CMOS devices are used for digital logic, while the high-voltage CMOS devices are used in the analog portion of the circuit design, including providing power to flash memory devices. There is currently a desire that the high-voltage CMOS devices have a high breakdown voltage for system on a chip applications, for example greater than 10-volt breakdown voltages, to support programming and writing functions.
A problem currently exists with the high-voltage CMOS devices, in that as the low-voltage CMOS device technology scales in size, the breakdown voltages attainable by the high-voltage CMOS devices decreases due to process changes. Namely, as the gate length of the low-voltage CMOS devices decreases, and in turn the poly gate thickness of the high-voltage CMOS devices decreases, the manufacturing process is limited to lower source/drain implant energies and less effective anneal processes for low-voltage CMOS devices. Because high-voltage CMOS devices and low-voltage CMOS devices are on the same chip, what results is a more abrupt PN junction between the source/drain regions and the channel region, which in turn results in a higher electrical field, and thus lower breakdown voltage for the high-voltage CMOS devices. Unfortunately, the breakdown voltages achievable for the high-voltage CMOS devices having the abrupt PN junction are often insufficient.
Accordingly, what is needed in the art is a method for manufacturing CMOS devices that accommodates the continued desire to scale while providing improved breakdown voltage characteristics.